Gianfranco Ferrante
12Patents
2h-index
15Co-inventors
47Inventor score
Filing activity: Nov 8, 2006 → Jan 31, 2024
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7571362B2 | Method of managing fails in a non-volatile memory device and relative memory device | Physics | 8 | Active |
| US8014208B1 | Erase verification for flash memory | Physics | 3 | Active |
| US10860474B2 | Multilevel addressing | Physics | 0 | Active |
| US11132311B2 | Interface for memory having a cache and multiple independent arrays | Physics | 0 | Active |
| US11768627B2 | Techniques for page line filler data | Physics | 0 | Active |
| US11461228B2 | Multilevel addressing | Physics | 0 | Active |
| US12360914B2 | Dynamic updates to logical-to-physical address translation table bitmaps | Physics | 0 | Active |
| US11556275B2 | Techniques for page line filler data | Physics | 0 | Active |
| US10175908B2 | Systems and methods for providing file information in a memory system protocol | Physics | 0 | Active |
| US9880772B2 | Systems and methods for providing file information in a memory system protocol | Physics | 0 | Active |
| US10534731B2 | Interface for memory having a cache and multiple independent arrays | Physics | 0 | Active |
| US11928063B1 | Dynamic updates to logical-to-physical address translation table bitmaps | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.