Interface for memory having a cache and multiple independent arrays
US10534731B2 · kind B2 · utility
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2References
33Claims
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Assignee
Inventors
Key dates
| Filing date | Mar 19, 2018 |
| Grant date | Jan 14, 2020 |
| Priority date | — |
| Expiry date | Mar 19, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2245
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure includes an interface for memory having a cache and multiple independent arrays. An embodiment includes a memory device having a cache and a plurality independent memory arrays, a controller, and an interface configured to communicate a plurality of commands from the controller to the memory device, wherein the interface includes a pin configured to activate upon a first one of the plurality of commands being received by the memory device and deactivate once all of the plurality of commands have been executed by the memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.