Disaggregation of SOC architecture
US10803548B2 · kind B2 · utility
19Cited by
1References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 15, 2019 |
| Grant date | Oct 13, 2020 |
| Priority date | — |
| Expiry date | Mar 15, 2039 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments described herein provide techniques to disaggregate an architecture of a system on a chip integrated circuit into multiple distinct chiplets that can be packaged onto a common chassis. In one embodiment, a graphics processing unit or parallel processor is composed from diverse silicon chiplets that are separately manufactured. A chiplet is an at least partially packaged integrated circuit that includes distinct units of logic that can be assembled with other chiplets into a larger package. A diverse set of chiplets with different IP core logic can be assembled into a single device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.