Lithography aware timing analysis
US8473876B2 · kind B2 · utility
1Cited by
6References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 20, 2007 |
| Grant date | Jun 25, 2013 |
| Priority date | — |
| Expiry date | Jul 20, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3312
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for performing timing analysis includes receiving information specifying an integrated circuit. A neighborhood of shapes associated with the integrated circuit is then determined. Delay information associated with the integrated circuit is generated based on the neighborhood of shapes. The neighborhood of shapes may be determined by determining a first set of spacings to a boundary of a first cell from an internal shape. A second set of spacings may be determined from the boundary of the first cell to a shape of a second cell. A lithography process may be characterized using the first and second set of spacings.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.