High performance PD SOI tunneling-biased MOSFET
US6518105B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 10, 2001 |
| Grant date | Feb 11, 2003 |
| Priority date | — |
| Expiry date | Dec 10, 2021 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/979
Abstract
A new type of partially-depleted SOI MOSFET is described in which a tunneling connection between the gate and the base is introduced. This is achieved by using a gate dielectric whose thickness is below its tunneling threshold. The gate pedestal is made somewhat longer than normal and a region near one end is implanted to be P+ (or N+ in a PMOS device). This allows holes (electrons for PMOS) to tunnel from gate to base. Since the hole current is self limiting, applied voltages greater than 0.7 volts may be used without incurring excessive leakage (as is the case with prior art DTMOS devices). A process for manufacturing the device is also described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.