Method for selective re-routing of selected areas in a target layer and in adjacent interconnecting layers of an IC device
US10002827B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 14, 2017 |
| Grant date | Jun 19, 2018 |
| Priority date | — |
| Expiry date | Mar 14, 2037 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P90/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods for identification and partial re-routing of selected areas (e.g., including critical areas) in a layout of an IC design and the resulting device are disclosed. Embodiments include comparing design data of an IC device against criteria of manufacturing processes to manufacture the IC device; identifying in the design data a layout area based, at least in part, on proximity of metal segments, interconnecting segments, or a combination thereof in the layout area; performing partial re-routing in the layout area to substantially meet the criteria, wherein at least one interconnecting element is shifted or extended; and integrating the partial re-routing into the design data for use in the manufacturing processes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.