Paul Ackmann
35Patents
6h-index
40Co-inventors
69Inventor score
Filing activity: Nov 3, 1983 → Jan 11, 2021
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6405144B1 | Method and apparatus for programmed latency for improving wafer-to-wafer uniformity | Electricity | 44 | Expired |
| US5757673A | Automated data management system for analysis and control of photolithography stepper performance | Emerging Cross-Sectional Technologies | 24 | Expired |
| US4508815A | Recessed metallization | Electricity | 22 | Expired |
| US5586059A | Automated data management system for analysis and control of photolithography stepper performance | Emerging Cross-Sectional Technologies | 21 | Expired |
| US6271602A | Method for reducing the susceptibility to chemical-mechanical polishing damage of an alignment mark formed in a semiconductor substrate | Electricity | 21 | Expired |
| US6207966A | Mark protection with transparent film | Electricity | 9 | Expired |
| US8010915B2 | Grid-based fragmentation for optical proximity correction in photolithography mask applications | Physics | 4 | Active |
| US8907496B1 | Circuit structures and methods of fabrication with enhanced contact via electrical connection | Electricity | 4 | Active |
| US6178256A | Removal of reticle effect on critical dimension by reticle rotation | Physics | 3 | Expired |
| US9500945B1 | Pattern classification based proximity corrections for reticle fabrication | Physics | 2 | Active |
| US9817927B2 | Hard mask etch and dielectric etch aware overlap for via and metal layers | Physics | 2 | Active |
| US9236301B2 | Customized alleviation of stresses generated by through-substrate via(S) | Electricity | 1 | Active |
| US9250538B2 | Efficient optical proximity correction repair flow method and apparatus | Physics | 1 | Active |
| US9029855B2 | Layout for reticle and wafer scanning electron microscope registration or overlay measurements | Electricity | 1 | Active |
| US10002827B2 | Method for selective re-routing of selected areas in a target layer and in adjacent interconnecting layers of an IC device | Emerging Cross-Sectional Technologies | 1 | Active |
| US9368453B2 | Overlay mark dependent dummy fill to mitigate gate height variation | Electricity | 1 | Active |
| US9323882B2 | Metrology pattern layout and method of use thereof | Physics | 0 | Active |
| US10401724B2 | Pellicle replacement in EUV mask flow | Physics | 0 | Active |
| US9864831B2 | Metrology pattern layout and method of use thereof | Physics | 0 | Active |
| US10816483B2 | Double pass diluted ultraviolet reticle inspection | Physics | 0 | Active |
| US9341961B2 | Cross technology reticle (CTR) or multi-layer reticle (MLR) CDU, registration, and overlay techniques | Physics | 0 | Active |
| US9798238B2 | Cross technology reticle (CTR) or multi-layer reticle (MLR) CDU, registration, and overlay techniques | Physics | 0 | Active |
| US9658531B2 | Semiconductor device resolution enhancement by etching multiple sides of a mask | Physics | 0 | Active |
| US10923388B2 | Gap fill void and connection structures | Electricity | 0 | Active |
| US9672313B2 | Method for selective re-routing of selected areas in a target layer and in adjacent interconnecting layers of an IC device | Emerging Cross-Sectional Technologies | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.