Laminated spacers for field-effect transistors
US10008456B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 27, 2017 |
| Grant date | Jun 26, 2018 |
| Priority date | — |
| Expiry date | Mar 27, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2021/6009
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Structures for spacers in a device structure for a field-effect transistor and methods for forming spacers in a device structure for a field-effect transistor. First and second spacers are formed adjacent to a surface of a device component from respective conformal layers. The first spacer is positioned between the surface of the device component and the second spacer. The second spacer includes a plurality of first lamina and a plurality of second lamina that are arranged in an alternating sequence with the first lamina. The first spacer has a first dielectric constant, and the second spacer has a second dielectric constant that is greater than the first dielectric constant.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.