Patent · US Active

Method for testing semiconductor dies

US10018667B2 · kind B2 · utility

0Cited by

2References

13Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Erwin Thalmann · Birkenfeld, DE
Michael Leutschacher · Finkenstein, AT
Christian Musshoff · Villach, AT
Stefan Kramp · Villach, AT

Key dates

Filing date	Aug 17, 2016
Grant date	Jul 10, 2018
Priority date	—
Expiry date	Oct 19, 2036

Classification

Technology area (CPC G)Physics
CPC primaryG01R31/2637
WIPO fieldMeasurement
WIPO sectorInstruments

Abstract

A method for testing semiconductor dies includes: providing a test apparatus; providing an electrically conductive carrier; providing a semiconductor substrate having a first main face, a second main face opposite to the first main face, and a plurality of semiconductor dies, the semiconductor dies including a first contact element on the first main face and a second contact element on the second main face; placing the semiconductor substrate on the carrier with the second main face facing the carrier; electrically connecting the carrier to a contact location disposed on the first main face; and testing a first semiconductor die of the plurality of semiconductor dies by electrically connecting the test apparatus with the first contact element of the first semiconductor die and the contact location.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.