Patent · US Active

Location-based optimization for memory systems

US10020031B2 · kind B2 · utility

0Cited by

10References

17Claims

0Family size

Assignee

Arm Limited · GB

Inventors

Yew Keong Chong · Austin, US
Andy Wangkun Chen · Austin, US
Sriram Thyagarajan · Austin, US
Gus Yeung · Austin, US
James Dennis Dodrill · Austin, US

Key dates

Filing date	Jan 9, 2017
Grant date	Jul 10, 2018
Priority date	—
Expiry date	Jan 9, 2037

Classification

Technology area (CPC G)Physics
CPC primaryG11C29/702
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Various implementations described herein are directed to a method of integrated circuit design and fabrication. In the implementation of a memory integrated circuit, the floorplan of the integrated circuit comprises memory blocks, where instantiations of the memory blocks are optimized to satisfy timing specifications while minimizing power consumption or not significantly contributing to leakage current.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.