Six-transistor static random access memory cell and operation method thereof
US10020049B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 24, 2017 |
| Grant date | Jul 10, 2018 |
| Priority date | — |
| Expiry date | Feb 18, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/418
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides a six transistor static random-access memory (6T-SRAM) cell, the 6T-SRAM cell includes a first inverter comprising a first pull-up transistor and a first pull-down transistor, and a first storage node, a second inverter comprising a second pull-up transistor, a second pull-down transistor, and a second storage node, wherein the first storage node is coupled to gates of the second pull-up transistor and the second pull-down transistor, a switch transistor configured to couple the second storage node to gates of the first pull-up transistor and the first pull-down transistor, and an access transistor coupled to gates of the first pull-up transistor and the first pull-down transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.