Yu-Tse Kuo
46Patents
5h-index
55Co-inventors
68Inventor score
Filing activity: Nov 2, 2011 → Jun 27, 2024
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US9761302B1 | Static random access memory cell and manufacturing method thereof | Electricity | 13 | Active |
| US9728541B1 | Static random-access memory (SRAM) cell array and forming method thereof | Electricity | 11 | Active |
| US9379119B1 | Static random access memory | Electricity | 9 | Active |
| US9698047B2 | Dummy gate technology to avoid shorting circuit | Electricity | 7 | Active |
| US10706914B2 | Static random access memory | Physics | 5 | Active |
| US9401366B1 | Layout pattern for 8T-SRAM and the manufacturing method thereof | Electricity | 5 | Active |
| US10559573B2 | Static random access memory structure | Electricity | 5 | Active |
| US9871048B1 | Memory device | Electricity | 5 | Active |
| US9786647B1 | Semiconductor layout structure | Electricity | 4 | Active |
| US10068909B1 | Layout pattern of a memory device formed by static random access memory | Electricity | 4 | Active |
| US10381056B2 | Dual port static random access memory (DPSRAM) cell | Electricity | 4 | Active |
| US10529723B2 | Layout pattern for static random access memory | Electricity | 3 | Active |
| US10847521B2 | Layout pattern of a static random access memory | Electricity | 3 | Active |
| US11475953B1 | Semiconductor layout pattern and forming method thereof | Electricity | 2 | Active |
| US10026726B2 | Dummy gate technology to avoid shorting circuit | Electricity | 2 | Active |
| US10861549B1 | Ternary content addressable memory unit capable of reducing charge sharing effect | Electricity | 2 | Active |
| US10153287B1 | Layout pattern for static random access memory | Electricity | 2 | Active |
| US10522551B2 | Semiconductor device and semiconductor apparatus | Electricity | 1 | Active |
| US9859282B1 | Semiconductor structure | Electricity | 1 | Active |
| US10366756B1 | Control circuit used for ternary content-addressable memory with two logic units | Physics | 1 | Active |
| US9953988B2 | Method of forming static random-access memory (SRAM) cell array | Electricity | 1 | Active |
| US9941288B2 | Static random-access memory (SRAM) cell array | Electricity | 1 | Active |
| US10892013B2 | Two-port ternary content addressable memory and layout pattern thereof, and associated memory device | Physics | 1 | Active |
| US9947674B2 | Static random-access memory (SRAM) cell array | Electricity | 1 | Active |
| US11943935B2 | Layout pattern of magnetoresistive random access memory | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.