Method of etching the back of a wafer to expose TSVs

US10026660B2 · kind B2 · utility

Assignee

• VEECO PRECISION SURFACE PROCESSING LLC · US

Inventors

• Laura Mauer · South Kent, US
• John Taddei · Jim Thorpe, US
• John Clark · Pflugerville, US
• Elena Lawrence · Norristown, US
• Eric Kurt Zwirnmann · Horsham, US
• David Goldberg · Palo Alto, US
• Jonathan Yutkowitz · Horsham, US

Key dates

• Filing date: Oct 30, 2015
• Grant date: Jul 17, 2018
• Expiry date: Jan 19, 2036

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L22/20
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A system and method for performing a wet etching process is disclosed. The system includes multiple processing stations accessible by a transfer device, including a measuring station to optically measure the thickness of a wafer before and after each etching steps in the process. The system also includes a controller to analyze the thickness measurements in view of a target wafer profile and generate an etch recipe, dynamically and in real time, for each etching step. In addition, the process controller can cause a single wafer wet etching station to etch the wafer according to the generated etching recipes. In addition, the system can, based on the pre and post-etch thickness measurements and target etch profile, generate and/or refine the etch recipes.