Multi-gate vertical field effect transistor with channel strips laterally confined by gate dielectric layers, and method of making thereof
US10032908B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 6, 2017 |
| Grant date | Jul 24, 2018 |
| Priority date | — |
| Expiry date | Jan 6, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/518
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A matrix rail structure is formed over a substrate. The matrix rail structure includes a pair of lengthwise sidewalls that extend along a first horizontal direction and comprises, or is at least partially subsequently replaced with, a set of at least one gate electrode rail extending along the first horizontal direction and straight-sidewalled gate dielectrics. A pair of vertical semiconductor channel strips and a pair of laterally-undulating gate dielectrics can be formed on sidewalls of the matrix rail structure for each vertical field effect transistor. At least one laterally-undulating gate electrode extending along the first horizontal direction is formed on the laterally-undulating gate dielectrics. Bottom active regions and top active regions are formed at end portions of the vertical semiconductor channel strips. The vertical field effect transistors can be formed as a two-dimensional array, and may be employed as access transistors for a three-dimensional memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.