Operation of a multi-slice processor implementing a load/store unit maintaining rejected instructions
US10037229B2 · kind B2 · utility
6Cited by
136References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 11, 2016 |
| Grant date | Jul 31, 2018 |
| Priority date | — |
| Expiry date | Aug 28, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/452
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Operation of a multi-slice processor that includes a plurality of execution slices, a plurality of load/store slices, and one or more instruction sequencing units, where operation includes: receiving, at a load/store slice from an instruction sequencing unit, a instruction to be issued; determining, at the load/store slice, a rejection condition for the instruction; and responsive to determining the rejection condition for the instruction, maintaining state information for the instruction in the load/store slice instead of notifying the instruction sequencing unit of a rejection of the instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.