Semiconductor device with a conductive post
US10049893B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 8, 2017 |
| Grant date | Aug 14, 2018 |
| Priority date | — |
| Expiry date | Mar 8, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2203/1316
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package comprises a substrate, a pad, a first isolation layer, an interconnection layer, and a conductive post. The substrate has a first surface and a second surface opposite the first surface. The pad has a first portion and a second portion on the first surface of the substrate. The first isolation layer is disposed on the first surface and covers the first portion of the pad, and the first isolation layer has a top surface. The interconnection layer is disposed on the second portion of the pad and has a top surface. The conductive post is disposed on the top surface of the first isolation layer and on the top surface of the interconnection layer. The top surface of the first isolation layer and the top surface of the interconnection layer are substantially coplanar.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.