Static random-access memory device
US10050044B2 · kind B2 · utility
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2References
14Claims
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Key dates
| Filing date | Feb 2, 2017 |
| Grant date | Aug 14, 2018 |
| Priority date | — |
| Expiry date | Feb 2, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/853
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention proposes a static random-access memory device (SRAM). The static random-access memory device is composed of two P-channel gates of loading transistor, two N-channel gates of driving transistor and two N-channel gates of accessing transistor in a memory cell. A dummy gate is disposed adjacent to the N-channel gate of accessing transistor with a bit line node disposed therebetween, wherein the dummy gate is electrically connected to a ground voltage through a metal layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.