Instruction and logic for bulk register reclamation
US10061587B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 25, 2014 |
| Grant date | Aug 28, 2018 |
| Priority date | — |
| Expiry date | Oct 17, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3858
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor includes a front end, a decoder, an allocator, and a retirement unit. The decoder includes logic to identify an end-of-live-range (EOLR) indicator. The EOLR indicator specifies an architectural register and a location in code for which the architectural register is unused. The allocator includes logic to scan for a mapping of the architectural register to a physical register, based upon the EOLR indicator. The allocator also includes logic to generate a request to disassociate the architectural register from the physical register. The retirement unit includes logic to disassociate the architectural register from the physical register.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.