FinFET device having a high germanium content fin structure and method of making same
US10062714B2 · kind B2 · utility
2Cited by
3References
5Claims
0Family size
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Key dates
| Filing date | Jun 9, 2016 |
| Grant date | Aug 28, 2018 |
| Priority date | — |
| Expiry date | Aug 2, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/822
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A fin of silicon-germanium material is formed and covered with an epitaxially grown layer of silicon material. A dummy transistor gate is then formed to extend over a channel of the fin. Sidewall spacers are formed on each side of the dummy transistor gate and directly on top of the expitaxial silicon layer. Epitaxially grown raised source and drain regions are formed on each side of the dummy transistor gate adjacent the sidewall spacers. The dummy transistor gate and a portion of the epitaxial silicon layer (underneath said dummy transistor gate) are removed and replaced by a metal gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.