Flatness of memory cell surfaces
US10062845B1 · kind B1 · utility
4Cited by
20References
20Claims
0Family size
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Key dates
| Filing date | May 11, 2017 |
| Grant date | Aug 28, 2018 |
| Priority date | — |
| Expiry date | May 11, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/884
Abstract
A two-terminal memory device can be formed according to a manufacturing process that utilizes two distinct chemical-mechanical planarization (CMP) processes for each of bottom electrode/terminal (BE) and the top electrode/terminal (TE). The CMP processes can reduce planar height variations for a top surface of the BE and a top surface of the TE. The CMP processes can reduce height differences between the top surface of the BE and adjacent dielectric surfaces and reduce height differences between the top surface of the TE and adjacent dielectric surfaces.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.