Natividad Vasquez
23Patents
7h-index
16Co-inventors
62Inventor score
Filing activity: Feb 19, 2009 → Mar 31, 2021
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US8946667B1 | Barrier structure for a silver based RRAM and method | Electricity | 24 | Active |
| US9166163B2 | Sub-oxide interface layer for two-terminal memory | Electricity | 23 | Active |
| US9595670B1 | Resistive random access memory (RRAM) cell and method for forming the RRAM cell | Electricity | 17 | Active |
| US9741765B1 | Monolithically integrated resistive memory using integrated-circuit foundry compatible processes | Electricity | 12 | Active |
| US9339630B2 | Retractable drug delivery system and method | Human Necessities | 9 | Active |
| US9412790B1 | Scalable RRAM device architecture for a non-volatile memory device and method | Electricity | 8 | Active |
| US9583701B1 | Methods for fabricating resistive memory device switching material using ion implantation | Electricity | 8 | Active |
| US10319908B2 | Integrative resistive memory in backend metal layers | Electricity | 6 | Active |
| US9425046B1 | Method for surface roughness reduction after silicon germanium thin film deposition | Electricity | 5 | Active |
| US9437814B1 | Mitigating damage from a chemical mechanical planarization process | Electricity | 5 | Active |
| US10062845B1 | Flatness of memory cell surfaces | Electricity | 4 | Active |
| US8716098B1 | Selective removal method and structure of silver in resistive switching device for a non-volatile memory device | Electricity | 4 | Active |
| US10290801B2 | Scalable silicon based resistive memory device | Electricity | 2 | Active |
| US10522754B2 | Liner layer for dielectric block layer | Electricity | 2 | Active |
| US9601690B1 | Sub-oxide interface layer for two-terminal memory | Electricity | 1 | Active |
| US11944020B2 | Using aluminum as etch stop layer | Electricity | 0 | Active |
| US10096653B2 | Monolithically integrated resistive memory using integrated-circuit foundry compatible processes | Electricity | 0 | Active |
| US10873023B2 | Using aluminum as etch stop layer | Electricity | 0 | Active |
| US10115819B2 | Recessed high voltage metal oxide semiconductor transistor for RRAM cell | Electricity | 0 | Active |
| US10749110B1 | Memory stack liner comprising dielectric block layer material | Electricity | 0 | Active |
| US11997932B2 | Resistive switching memory having confined filament formation and methods thereof | Electricity | 0 | Active |
| US12075712B2 | Resistive switching memory devices and method(s) for forming the resistive switching memory devices | Electricity | 0 | Active |
| US10192927B1 | Semiconductor device for a non-volatile (NV) resistive memory and array structure for an array of NV resistive memory | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.