Efficient enforcement of barriers with respect to memory move sequences
US10067713B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 22, 2016 |
| Grant date | Sep 4, 2018 |
| Priority date | — |
| Expiry date | Sep 2, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/60
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a data processing system implementing a weak memory model, a lower level cache receives, from a processor core, a plurality of copy-type requests and a plurality of paste-type requests that together indicate a memory move to be performed. The lower level cache also receives, from the processor core, a barrier request that requests enforcement of ordering of memory access requests prior to the barrier request with respect to memory access requests after the barrier request. In response to the barrier request, the lower level cache enforces a barrier indicated by the barrier request with respect to a final paste-type request ending the memory move but not with respect to other copy-type requests and paste-type requests in the memory move.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.