Patent · US Active

Overflow detection for sign-magnitude adders

US10067744B2 · kind B2 · utility

0Cited by

8References

16Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Petra Leber · Ehningen, DE
Cedric Lichtenau · Stuttgart, DE
Silvia M. Mueller · Altdorf, DE

Key dates

Filing date	Dec 8, 2016
Grant date	Sep 4, 2018
Priority date	—
Expiry date	Dec 8, 2036

Classification

Technology area (CPC G)Physics
CPC primaryG06F7/505
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A circuit is provided which includes arithmetic computation logic configured to add or subtract operands of variable length to produce a result in a sign-magnitude data format. The circuit also includes an overflow detector to provide an overflow signal indicative of whether the result fits within a specified result length l. The overflow detector operates on the operands prior to the arithmetic computation logic producing the result to determine, independent of the result produced by the arithmetic computation logic, whether the result fits within the specified result length l.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.