Method for direct integration of memory die to logic die without use of thru silicon vias (TSV)
US10068874B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 16, 2014 |
| Grant date | Sep 4, 2018 |
| Priority date | — |
| Expiry date | Jun 16, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1436
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method including forming a first substrate including an integrated circuit device layer disposed between a plurality of first interconnects and a plurality of second interconnects; coupling a second substrate including a memory device layer to the first substrate so that the memory device layer is juxtaposed to one of the plurality of first interconnects and the plurality of second interconnects; and removing a portion of the first substrate. An apparatus including a device layer including a plurality of circuit devices disposed between a plurality of first interconnects and a plurality of second interconnects on a substrate; a memory device layer including a plurality of memory devices juxtaposed and coupled to one of the plurality of first interconnects and the plurality of second interconnects; and contacts points coupled to one of ones of the first plurality of interconnects and ones of the second plurality of interconnects.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.