Layout pattern of a memory device formed by static random access memory
US10068909B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 27, 2017 |
| Grant date | Sep 4, 2018 |
| Priority date | — |
| Expiry date | Oct 27, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/83
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides a layout pattern of a memory device composed of static random access memory (SRAM), comprising four memory units located on a substrate, each memory unit being located in a non-rectangular region, the four non-rectangular regions combine a rectangular region, wherein each memory unit comprises a first inverter comprising a first pull-up transistor (PL1) and a first pull-down transistor (PD1), a second inverter comprises a second pull-up transistor (PL2) and a second pull-down transistor (PD2), an access transistor (PG) and a switching transistor (SW), wherein the source of the PG is coupled to an input terminal of the first inverter and a drain of the SW, a source of the SW is coupled to an output of the second inverter, wherein the PD1, the PD2, the SW, and the PG comprise a first diffusion region, the PL1 and the PL2 comprise a second diffusion region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.