Alignment testing for tiered semiconductor structure
US10073135B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 22, 2017 |
| Grant date | Sep 11, 2018 |
| Priority date | — |
| Expiry date | May 22, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/54
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Among other things, one or more techniques or systems for evaluating a tiered semiconductor structure, such as a stacked CMOS structure, for misalignment are provided. In an embodiment, a connectivity test is performed on vias between a first layer and a second layer to determine a via diameter and a via offset that are used to evaluate misalignment. In an embodiment, a connectivity test for vias within a first layer is performed to determine an alignment rotation based upon which vias are connected through a conductive arc within a second layer or which vias are connected to a conductive pattern out of a set of conductive patterns. In this way, the via diameter, the via offset, or the alignment rotation are used to evaluate the tiered semiconductor structure, such as during a stacked CMOS process, for misalignment.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.