Logic and flash field-effect transistors

US10079242B2 · kind B2 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Ralf Richter · Dresden, DE
• Thomas Melde · Dresden, DE
• Elke Erben · Dresden, DE

Key dates

• Filing date: Dec 1, 2016
• Grant date: Sep 18, 2018
• Expiry date: Dec 1, 2036

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/6736

Abstract

Methods of forming a device structure for a field-effect transistor and device structures for a field-effect transistor. A first gate dielectric layer is formed on a semiconductor layer in a first area. A hardmask layer is formed on the first gate dielectric layer in the first area of the semiconductor layer. A gate stack layer is formed on the semiconductor layer in a second area and on the hardmask layer in the first area of the semiconductor layer. The hardmask layer separates the gate stack layer from the first gate dielectric layer on the first area of the semiconductor layer.