Self aligned top extension formation for vertical transistors
US10079299B2 · kind B2 · utility
8Cited by
5References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Jun 19, 2017 |
| Grant date | Sep 18, 2018 |
| Priority date | — |
| Expiry date | Jun 28, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/822
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a semiconductor device that includes providing a vertically orientated channel region; and converting a portion of an exposed source/drain contact surface of the vertically orientated channel region into an amorphous crystalline structure. The amorphous crystalline structure is from the vertically orientated channel region. An in-situ doped extension region is epitaxially formed on an exposed surface of the vertically orientated channel region. A source/drain region is epitaxially formed on the in-situ doped extension region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.