Computer implemented system and method for generating a layout of a cell defining a circuit component
US10083269B2 · kind B2 · utility
Assignee
Inventors
- Paul Christopher de Dood
- Marlin Wayne Frederick, Jr.
- Jerry C. Wang
- Brian Lee
- Brian Tracy Cline
- Xiaoqing Xu
- Andy Wangkun Chen
- Yew Keong Chong
- Tom Shore
- Sriram Thyagarajan
- Gus Yeung
- Yanbin Jiang
- Emmanuel Jean Marie Olivier Pacaud
- Matthieu Domonique Henri Pauly
- Sylvia Xiuhui Li
- Thanusree Achuthan
- Daniel J. Albers
- David William Granda
Key dates
| Filing date | Oct 30, 2014 |
| Grant date | Sep 25, 2018 |
| Priority date | — |
| Expiry date | Feb 23, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2111/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer implemented system and method is provided for generating a layout of the cell defining a circuit component, the layout providing a layout pattern for a target process technology. The method comprises obtaining an archetype layout providing a valid layout pattern for the cell having regard to design rules of the target process technology, and receiving an input data file providing a process technology independent schematic of the circuit component for which the cell is to be generated. A schematic sizing operation is then performed on the input data file, having regard to both schematic constraints applicable to the target process technology and layout constraints derived from the archetype layout, in order to generate an output data file providing a process technology dependent schematic of the circuit component. A cell generation operation is then performed using the output data file and layout data determined from the archetype layout in order to generate the layout of the cell. Such an approach enables both the schematic and layout to be co-optimized during generation of the layout of the cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.