Fabrication of a vertical transistor with self-aligned bottom source/drain

US10083871B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Kangguo Cheng · Schenectady, US
• Xin Miao · Guilderland, US
• Wenyu Xu · Albany, US
• Chen Zhang · Guilderland, US

Key dates

• Filing date: Jun 9, 2016
• Grant date: Sep 25, 2018
• Expiry date: Jun 9, 2036

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/83
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method of forming a vertical fin field effect transistor (vertical finFET) with a self-aligned bottom source/drain, including forming a doped layer on a substrate, forming one or more vertical fins on the doped layer, forming a protective layer on the one or more vertical fins, wherein the protective layer has a thickness, and forming at least one isolation trench by removing at least a portion of the protective layer on the doped layer, wherein the isolation trench is laterally offset from at least one of the one or more vertical fins by the thickness of the protective layer.