Gate cut method
US10083874B1 · kind B1 · utility
23Cited by
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18Claims
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Key dates
| Filing date | Mar 23, 2017 |
| Grant date | Sep 25, 2018 |
| Priority date | — |
| Expiry date | Mar 23, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0179
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a FinFET structure involves forming gate cuts within a sacrificial gate layer prior to patterning and etching the sacrificial gate layer to form longitudinal sacrificial gate structures. By forming transverse cuts in the sacrificial gate layer before defining the sacrificial gate structures longitudinally, dimensional precision of the gate cuts at lower critical dimensions can be improved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.