Enhanced dislocation stress transistor
US10084087B2 · kind B2 · utility
0Cited by
2References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 17, 2017 |
| Grant date | Sep 25, 2018 |
| Priority date | — |
| Expiry date | Apr 17, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/259
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A device is provided. The device includes a transistor formed on a semiconductor substrate, the transistor having a conduction channel. The device includes at least one edge dislocation formed adjacent to the conduction channel on the semiconductor substrate. The device also includes at least one free surface introduced above the conduction channel and the at least one edge dislocation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.