Integrated system and method for source/drain engineering
US10090147B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 6, 2018 |
| Grant date | Oct 2, 2018 |
| Priority date | — |
| Expiry date | Feb 6, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/021
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Implementations described herein generally provide a method of processing a substrate. Specifically, the methods described are used for cleaning and etching source/drain regions on a silicon substrate in preparation for precise Group IV source/drain growth in semiconductor devices. Benefits of this disclosure include precise fin size control in devices, such as 10 nm FinFET devices, and increased overall device yield. The method of integrated clean and recess includes establishing a low pressure processing environment in the processing volume, and maintaining the low pressure processing environment while flowing a first gas over a substrate in a processing volume, depositing a salt on the substrate, heating the processing volume to greater than 90° C., purging the processing volume with a second inert gas, and recessing a source/drain region disposed on the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.