Flip chip interconnection with reduced current density
US10090274B2 · kind B2 · utility
1Cited by
1References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 24, 2015 |
| Grant date | Oct 2, 2018 |
| Priority date | — |
| Expiry date | Nov 23, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/10166
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method and system for electrically connect a semiconductor device with a flip-chip form factor to a printed circuit board. An exemplary embodiment of the method comprises: aligning solder contacts on the device with a first copper contact and a second copper contact of the external circuitry, and, applying a supply current only directly to a buried layer of the first copper and not directly to the layer which is nearest the device, such that no current is sourced to the device through the layer nearest the device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.