Tiled-stress-alleviating pad structure
US10096557B2 · kind B2 · utility
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10Claims
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Key dates
| Filing date | Oct 24, 2017 |
| Grant date | Oct 9, 2018 |
| Priority date | — |
| Expiry date | Oct 24, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/351
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Structure and method for reducing thermal-mechanical stresses generated for a semiconductor device are provided, which includes a tiled-stress-alleviating pad structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.