Monolithically integrated resistive memory using integrated-circuit foundry compatible processes
US10096653B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 31, 2014 |
| Grant date | Oct 9, 2018 |
| Priority date | — |
| Expiry date | Jul 27, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B63/30
Abstract
Provided is a monolithic integration of resistive memory with complementary metal oxide semiconductor using integrated circuit foundry processes. A memory device is provided that includes a substrate comprising one or more complementary metal-oxide semiconductor devices, a first insulator layer formed on the substrate; and a monolithic stack. The monolithic stack includes multiple layers fabricated as part of a monolithic process over the first insulator layer. The multiple layers include a first metal layer, a second insulator layer, and a second metal layer. A resistive memory device structure is formed within the second insulator layer and within a thermal budget of the one or more complementary metal-oxide semiconductor devices. The resistive memory device structure is implemented as a pillar device or as a via device. Further, the first metal layer is coupled to the second metal layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.