Multi-step surface passivation structures and methods for fabricating same
US10096702B2 · kind B2 · utility
3Cited by
2References
24Claims
0Family size
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Key dates
| Filing date | May 31, 2017 |
| Grant date | Oct 9, 2018 |
| Priority date | — |
| Expiry date | May 31, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/343
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A gallium nitride (GaN) transistor which includes two or more insulator semiconductor interface regions (insulators). A first insulator disposed between the gate and drain (near the gate) minimizes the gate leakage and fields near the gate that cause high gate-drain charge (Qgd). A second insulator (or multiple insulators), disposed between the first insulator and the drain, minimizes electric fields at the drain contact and provides a high density of charge in the channel for low on-resistance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.