Aspect ratio trapping (ART) for fabricating vertical semiconductor devices

US10096709B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Van H. Le · Portland, US
• Benjamin Chu-Kung · Portland, US
• Gilbert Dewey · Beaverton, US
• Jack T. Kavalieros · Portland, US
• Ravi Pillarisetty · Portland, US
• Willy Rachmady · Beaverton, US
• Marko Radosavljevic · Portland, US
• Matthew V. Metz · Portland, US
• Niloy Mukherjee · Beaverton, US
• Robert S. Chau · Beaverton, US

Key dates

• Filing date: Mar 28, 2014
• Grant date: Oct 9, 2018
• Expiry date: Mar 28, 2034

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/038

Abstract

Aspect ratio trapping (ART) approaches for fabricating vertical semiconductor devices and vertical semiconductor devices fabricated there from are described. For example, a semiconductor device includes a substrate with an uppermost surface having a first lattice constant. A first source/drain region is disposed on the uppermost surface of the substrate and has a second, different, lattice constant. A vertical channel region is disposed on the first source/drain region. A second source/drain region is disposed on the vertical channel region. A gate stack is disposed on and completely surrounds a portion of the vertical channel region.