Replacement policies for a hybrid hierarchical cache

US10102149B1 · kind B1 · utility

Assignee

• Intel Corporation · US

Inventors

• Abhishek R. Appu · Cameron Park, US
• Joydeep Ray · Folsom, US
• James Valerio · Hillsboro, US
• Altug Koker · Cameron Park, US
• Prasoonkumar Surti · Folsom, US
• Balaji Vembu · Folsom, US
• Wenyin Fu · Folsom, US
• Bhushan M. Borole · Rancho Cordova, US
• Kamal Sinha · Rancho Cordova, US

Key dates

• Filing date: Apr 17, 2017
• Grant date: Oct 16, 2018
• Expiry date: Apr 17, 2037

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F2212/70
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A hybrid hierarchical cache is implemented at the same level in the access pipeline, to get the faster access behavior of a smaller cache and, at the same time, a higher hit rate at lower power for a larger cache, in some embodiments. A split cache at the same level in the access pipeline includes two caches that work together. In the hybrid, split, low level cache (e.g., L1) evictions are coordinated locally between the two L1 portions, and on a miss to both L1 portions, a line is allocated from a larger L2 cache to the smallest L1 cache.