Process for filling vias in the microelectronics

US10103029B2 · kind B2 · utility

Assignee

• MacDermid Enthone Inc. · US

Inventors

• Thomas B. Richardson · Waterbury, US
• Joseph A. Abys · Hackettstown, US
• Wenbo Shao · Stamford, US
• Chen Wang · New Haven, US
• Vincent Paneccasio, Jr. · Madison, US
• Cai Wang · Taipei, TW
• Sean Xuan Lin · Hopkins, US
• Theodore Antonellis · Bethany, US

Key dates

• Filing date: May 6, 2016
• Grant date: Oct 16, 2018
• Expiry date: May 6, 2036

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/76898
• WIPO field: Surface technology, coating
• WIPO sector: Chemistry

Abstract

A process for metalizing a through silicon via feature in a semiconductor integrated circuit device, the process including, during the filling cycle, reversing the polarity of circuit for an interval to generate an anodic potential at said metalizing substrate and desorb leveler from the copper surface within the via, followed by resuming copper deposition by re-establishing the surface of the copper within the via as the cathode in the circuit, thereby yielding a copper filled via feature.