Offset backside contact via structures for a three-dimensional memory device
US10103161B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 28, 2016 |
| Grant date | Oct 16, 2018 |
| Priority date | — |
| Expiry date | Oct 14, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/115
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Die cracking of a three dimensional memory device may be reduced by adding offsets to backside contact via structures. Each backside contact via structure can include laterally extending portions that extend along a first horizontal direction adjoined by adjoining portions that extend along a horizontal direction other than the first horizontal direction. In order to preserve periodicity of memory stack structures extending through an alternating stack of insulating layers and electrically conductive layers, the distance between an outermost row of a string of memory stack structures between a pair of backside contact via structures and a most proximal backside contact via structure can vary from a laterally extending portion to another laterally extending portion within the most proximal backside contact via structure. Source shunt lines that are parallel to bit lines can be formed over a selected subset of offset portions of the backside contact via structures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.