Multiple liner interconnects for three dimensional memory devices and method of making thereof
US10115459B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 29, 2017 |
| Grant date | Oct 30, 2018 |
| Priority date | — |
| Expiry date | Sep 29, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/75
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An opening is formed through at least one dielectric material layer. A first metallic liner is formed on a bottom surface and sidewalls of the opening by depositing a first metallic material. A metal portion including an elemental metal or an intermetallic alloy of at least two elemental metals is formed on the first metallic liner. A second metallic liner including a second metallic material is formed directly on a top surface of the metal portion. The first metallic material and the second metallic material differ in composition. The first metallic liner and the second metallic liner contact an entirety of all surfaces of the metal portion. The first and second metallic liners can protect the metal portion from a subsequently deposited dielectric material layer, which may be formed as an air-gap dielectric layer after recessing the at least one dielectric material layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.