Patent · US Active

Method for fabricating auto-aligned interconnection elements for a 3D integrated circuit

US10115637B2 · kind B2 · utility

2Cited by

10References

9Claims

0Family size

Assignee

COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES · FR

Inventors

Claire Fenouillet-Beranger · Grenoble, FR
Benoit Mathieu · Grenoble, FR
Philippe Coronel · Barraux, FR

Key dates

Filing date	Nov 22, 2017
Grant date	Oct 30, 2018
Priority date	—
Expiry date	Nov 22, 2037

Classification

Technology area (CPC H)Electricity
CPC primaryH10D88/00
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

Method for fabricating transistors for an integrated 3D circuit, comprising:

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.