Three dimensional memory device containing discrete silicon nitride charge storage regions
US10115732B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 22, 2016 |
| Grant date | Oct 30, 2018 |
| Priority date | — |
| Expiry date | Feb 22, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/693
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Discrete silicon nitride portions can be formed at each level of electrically conductive layers in an alternating stack of insulating layers and the electrically conductive layers. The discrete silicon nitride portions can be employed as charge trapping material portions, each of which is laterally contacted by a tunneling dielectric portion on the front side, and by a blocking dielectric portion on the back side. The tunneling dielectric portions may be formed as discrete material portions or portions within a tunneling dielectric layer. The blocking dielectric portions may be formed as discrete material portions or portions within a blocking dielectric layer. The discrete silicon nitride portions can be formed by depositing a charge trapping material layer and selectively removing portions of the charge trapping material layer at levels of the insulating layers. Various schemes may be employed to singulate the charge trapping material layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.