Patent · US Active

Memory devices and systems having reduced bit line to drain select gate shorting and associated methods

US10134758B2 · kind B2 · utility

4Cited by
1References
20Claims
0Family size

Assignee

Inventors

Key dates

Filing dateAug 22, 2017
Grant dateNov 20, 2018
Priority date—
Expiry dateAug 22, 2037

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH10B43/35
  • WIPO fieldComputer technology
  • WIPO sectorElectrical engineering

Abstract

3D NAND memory devices and systems having reduced bit line to drain select gate shorting, including associated methods, are provided and described.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.