Dual-layer dielectric in memory device

US10134809B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Michael J. Bernhardt · Boise, US
• Yudong Kim · Cupertino, US
• Denzil S. Frost · Lehi, US
• Tuman Earl Allen, III · Kuna, US
• Kevin Lee Baker · Boise, US
• Kolya Yastrebenetsky · Boise, US
• Ronald A. Weimer · Boise, US

Key dates

• Filing date: Jun 2, 2017
• Grant date: Nov 20, 2018
• Expiry date: Jun 2, 2037

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/15311
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Embodiments of the present disclosure describe techniques and configurations for a memory device comprising a memory array having a plurality of wordlines disposed in a memory region of a die. Fill regions may be disposed between respective pairs of adjacent wordlines of the plurality of wordlines. The fill regions may include a first dielectric layer and a second dielectric layer disposed on the first dielectric layer. The first dielectric layer may comprise organic (e.g., carbon-based) spin-on dielectric material (CSOD). The second dielectric layer may comprise a different dielectric material than the first dielectric layer, such as, for example, inorganic dielectric material. Other embodiments may be described and/or claimed.