Termination region architecture for vertical power transistors
US10134890B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 17, 2017 |
| Grant date | Nov 20, 2018 |
| Priority date | — |
| Expiry date | Oct 17, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/112
Abstract
A vertical power switching device, such as a vertical superjunction metal-oxide-semiconductor field-effect-transistor (MOSFET), in which termination structures in the corners of the integrated circuit are stretched to efficiently shape the lateral electric field. Termination structures in the device include such features as doped regions, field plates, insulator films, and high-voltage conductive regions and elements at the applied substrate voltage. Edges of these termination structures are shaped and placed according to a 2nd-order smooth, non-circular analytic function so as to extend deeper into the die corner from the core region of the device than a constant-distance path. Also disclosed are electrically floating guard rings in the termination region, to inhibit triggering of parasitic p-n-p-n structures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.