Method of forming flash memory with separate wordline and erase gates
US10141321B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 11, 2016 |
| Grant date | Nov 27, 2018 |
| Priority date | — |
| Expiry date | Oct 11, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0408
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of forming a non-volatile memory cell includes forming spaced apart first and second regions in a substrate, defining a channel region there between. A floating gate is formed over a first portion of the channel region and over a portion of the first region, wherein the floating gate includes a sharp edge disposed over the first region. A tunnel oxide layer is formed around the sharp edge. An erase gate is formed over the first region, wherein the erase gate includes a notch facing the sharp edge, and wherein the notch is insulated from the sharp edge by the tunnel oxide layer. A word line gate is formed over a second portion of the channel region which is adjacent to the second region. The forming of the word line gate is performed after the forming of the tunnel oxide layer and the erase gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.