Formation of bottom junction in vertical FET devices
US10141446B2 · kind B2 · utility
3Cited by
6References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 25, 2017 |
| Grant date | Nov 27, 2018 |
| Priority date | — |
| Expiry date | Oct 25, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6728
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Formation of a bottom junction in vertical FET devices may include, for instance, providing an intermediate semiconductor structure comprising a semiconductor substrate, a fin disposed on the semiconductor substrate. The fin has a top surface, spaced-apart vertical sides. A mask is disposed over the top surface of the fin, and at least one is disposed over the vertical sides of the fin. Portions of the substrate are removed to define spaced-apart recesses each extending below a respective one of the spacers. Semiconductor material is grown, such as epitaxially grown, in the recesses.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.