Daniel Chanemougame
101Patents
11h-index
63Co-inventors
79Inventor score
Filing activity: Feb 3, 2005 → Aug 30, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US10510620B1 | Work function metal patterning for N-P space between active nanostructures | Electricity | 54 | Active |
| US10192819B1 | Integrated circuit structure incorporating stacked field effect transistors | Electricity | 45 | Active |
| US10332803B1 | Hybrid gate-all-around (GAA) field effect transistor (FET) structure and method of forming | Electricity | 42 | Active |
| US10090193B1 | Integrated circuit structure incorporating a stacked pair of field effect transistors and a buried interconnect and method | Electricity | 35 | Active |
| US10026824B1 | Air-gap gate sidewall spacer and method | Electricity | 31 | Active |
| US10374040B1 | Method to form low resistance contact | Electricity | 21 | Active |
| US10566248B1 | Work function metal patterning for N-P spaces between active nanostructures using unitary isolation pillar | Electricity | 14 | Active |
| US10304832B1 | Integrated circuit structure incorporating stacked field effect transistors and method | Electricity | 13 | Active |
| US10304833B1 | Method of forming complementary nano-sheet/wire transistor devices with same depth contacts | Electricity | 13 | Active |
| US10236215B1 | Methods of forming gate contact structures and cross-coupled contact structures for transistor devices | Electricity | 13 | Active |
| US10170520B1 | Negative-capacitance steep-switch field effect transistor with integrated bi-stable resistive system | Electricity | 12 | Active |
| US9299721B2 | Method for making semiconductor device with different fin sets | Electricity | 10 | Active |
| US10388652B2 | Intergrated circuit structure including single diffusion break abutting end isolation region, and methods of forming same | Electricity | 9 | Active |
| US11201152B2 | Method, apparatus, and system for fin-over-nanosheet complementary field-effect-transistor | Electricity | 8 | Active |
| US10692991B2 | Gate-all-around field effect transistors with air-gap inner spacers and methods | Electricity | 7 | Active |
| US10290549B2 | Integrated circuit structure, gate all-around integrated circuit structure and methods of forming same | Electricity | 6 | Active |
| US10079173B2 | Methods of forming metallization lines on integrated circuit products and the resulting products | Electricity | 5 | Active |
| US10685874B1 | Self-aligned cuts in an interconnect structure | Electricity | 5 | Active |
| US9941162B1 | Self-aligned middle of the line (MOL) contacts | Electricity | 5 | Active |
| US10256316B1 | Steep-switch field effect transistor with integrated bi-stable resistive system | Electricity | 5 | Active |
| US10818792B2 | Nanosheet field-effect transistors formed with sacrificial spacers | Electricity | 4 | Active |
| US10651284B2 | Methods of forming gate contact structures and cross-coupled contact structures for transistor devices | Electricity | 4 | Active |
| US10141446B2 | Formation of bottom junction in vertical FET devices | Electricity | 3 | Active |
| US7229867B2 | Process for producing a field-effect transistor and transistor thus obtained | Electricity | 3 | Expired |
| US11264274B2 | Reverse contact and silicide process for three-dimensional logic devices | Electricity | 3 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.